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| RFG40N10, RFP40N10, RF1S40N10SM Data Sheet July 1999 File Number 2431.3 40A, 100V, 0.040 Ohm, N-Channel Power MOSFETs These are N-Channel power MOSFETs manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers, relay drivers and emitter switches for bipolar transistors. These transistors can be operated directly from integrated circuits. Formerly developmental type TA9846 Features * 40A, 100V * rDS(ON) = 0.040 * UIS Rating Curve * SOA is Power Dissipation Limited * 175oC Operating Temperature * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Symbol D Ordering Information PART NUMBER RFG40N10 RFP40N10 RF1S40N10SM PACKAGE TO-247 TO-220AB TO-263AB BRAND RFG40N10 RFP40N10 G S F1S40N10 NOTE: When ordering, use the entire part number. Add the suffix, 9A, to obtain the TO-263AB variant in tape and reel, i.e. RF1S40N10SM9A. Packaging JEDEC STYLE TO-247 SOURCE DRAIN GATE DRAIN (FLANGE) JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) JEDEC TO-263AB DRAIN (FLANGE) GATE SOURCE 4-450 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 RFG40N10, RFP40N10, RF1S40N10SM Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFG40N10, RFP40N10, RF1S40N10SM 100 100 20 40 100 Figures 4, 12, 13 160 1.07 -55 to 175 300 260 UNITS V V V A A W W/oC oC oC oC Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 1M) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, see Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. TJ = 25oC to 150oC. 2. Repetitive Rating: pulse width limited by maximum junction temperature. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V (Figure 9) VGS = VDS, ID = 250A (Figure 8) VDS = 80V, VGS = 0V VGS = 20V ID = 40A, VGS = 10V (Figure 7) VDD = 50V, ID = 20A, RL = 2.5, VGS = 10V, RGS = 4.2 (Figure 11) TC = 25oC TC = 150oC MIN 100 2 VGS = 0V to 20V VGS = 0V to 10V VGS = 0V to 2V VDD = 80V, ID = 40A, RL = 2.0 (Figures 11) TO-247 TO-220AB and TO-263AB TYP 17 30 42 20 MAX 4 1 50 100 0.040 80 100 300 150 7.5 0.94 30 62 UNITS V V A A nA ns ns ns ns ns ns nC nC nC oC/W oC/W oC/W Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On Resistance Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 10V Threshold Gate Charge Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(10) Qg(TH) RJC RJA Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Reverse Recovery Time SYMBOL VSD trr ISD = 40A ISD = 40A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.5 200 UNITS V ns 4-451 RFG40N10, RFP40N10, RF1S40N10SM Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 125 50 75 100 TC , CASE TEMPERATURE (oC) 150 175 ID, DRAIN CURRENT (A) Unless Otherwise Specified 40 32 24 16 8 0 25 50 75 100 125 150 175 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 100 VDSS(MAX) = 100V IAS, AVALANCHE CURRENT (A) ID , DRAIN CURRENT (A) TC = 25oC SINGLE PULSE TJ = MAX RATED DC OPERATION 100 ST AR TIN ST AR TIN GT J= 25 o 10 C GT J= 1 10 50 o C 1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) IF R = 0 tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD) IF R 0 tAV = (L/R) LN [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1] 0.1 1 10 0.1 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 100 1 0.01 tAV, TIME IN AVALANCHE (ms) FIGURE 3. FORWARD BIAS SAFE OPERATING AREA NOTE: Refer to Intersil application notes AN9321 and AN9322. FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 100 7V 100 GS =1 0 80 ID , DRAIN CURRENT (A) VG ID, DRAIN CURRENT (A) S = PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC 80 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V V -55oC 25oC 60 VGS = 6V 175oC 60 V 40 VGS = 5V 20 VGS = 4V 0 0 2 4 6 8 VDS, DRAIN TO SOURCE VOLTAGE (V) 10 40 20 0 0 2 4 6 8 10 VGS , GATE TO SOURCE VOLTAGE (V) FIGURE 5. SATURATION CHARACTERISTICS FIGURE 6. TRANSFER CHARACTERISTICS 4-452 RFG40N10, RFP40N10, RF1S40N10SM Typical Performance Curves 2.5 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 40A NORMALIZED GATE THRESHOLD VOLTAGE Unless Otherwise Specified (Continued) 1.50 1.25 1.00 0.75 0.50 0.25 VGS = VDS ID = 250A 2.0 1.5 1.0 0.5 0 -50 0 50 100 150 200 TJ, JUNCTION TEMPERATURE (oC) 0 -50 0 50 100 150 200 TJ, JUNCTION TEMPERATURE (oC) FIGURE 7. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 2.0 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A 6000 5000 C, CAPACITANCE (pF) 1.5 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD 4000 3000 2000 COSS 1000 CRSS 0 CISS 1.0 0.5 0 -50 0 50 100 150 200 TJ, JUNCTION TEMPERATURE (oC) 0 5 10 15 20 25 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 9. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 100 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 10. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 10 VGS, GATE TO SOURCE VOLTAGE (V) VDD = BVDSS 75 VDD = BVDSS 7.5 50 0.75 BVDSS 0.75 BVDSS 0.50 BVDSS 0.50 BVDSS 0.25 BVDSS 0.25 BVDSS RL = 2.5 Ig(REF) = 2.25mA VGS = 10V 0 20 5.0 25 2.5 0 Ig(REF) Ig(ACT) t, TIME (s) 80 Ig(REF) Ig(ACT) NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 11. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT 4-453 RFG40N10, RFP40N10, RF1S40N10SM Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + 0V IAS 0.01 0 tAV FIGURE 12. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 13. UNCLAMPED ENERGY WAVEFORMS tON td(ON) tr RL VDS + tOFF td(OFF) tf 90% 90% DUT RGS VDD 0 10% 90% 10% VGS VGS 0 10% 50% PULSE WIDTH 50% FIGURE 14. SWITCHING TIME TEST CIRCUIT FIGURE 15. RESISTIVE SWITCHING WAVEFORMS VDS RL VDD VDS VGS = 20V VGS + Qg(TOT) Qg(10) VDD VGS VGS = 2V 0 Qg(TH) Ig(REF) 0 VGS = 10V DUT Ig(REF) FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORMS 4-454 RFG40N10, RFP40N10, RF1S40N10SM All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 4-455 |
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